With the end of lithography scaling as a key driver for technology improvement and the end of Dennard scaling, improvements in application performance will increasingly come from customized memory hierarchies and accelerator devices. No matter what form the accelerators take, where they are located (edge or on-chip), or the composition of the memory hierarchies, the clear question remaining is how to deal with the complexity that awaits us in our not too distant future in a tractable way. Our presentation will outline an Arm vision for future system architecture for this post-Exascale era.